As a method for recording digital data on optical recording mediums such as a CD (Compact Disc) and a DVD (Digital Versatile Disc), there has commonly been employed a method in which digital data to be recorded are subjected to mark width modulation to make the track recording density constant, thereby to make the recording density on the disc uniform. When performing reproduction and demodulation of the digital data recorded by the above-mentioned recording method, the phase of a clock component corresponding to a channel bit frequency of a reproduction signal is detected, and phase sync pull-in is carried out by using a phase-locked loop.
At this time, if the frequency of the clock component possessed by the reproduction signal is significantly different from the frequency of the clock generated by the phase-locked loop, there is a high possibility of imperfect phase sync pull-in or pseudo pull-in into different frequencies. In order to solve these problems and realize normal phase sync pull-in, a reproduction linear velocity cycle is detected on the basis of a specific pulse length or pulse interval included in the reproduction signal, and the rotation speed of the disc or the free-running frequency of the phase-locked loop is controlled according to the reproduction linear velocity cycle.
FIG. 14 is a block diagram illustrating the construction of a conventional digital data reproduction apparatus. This digital data reproduction apparatus is able to perform normal phase sync pull-in, and normal offset correction in the amplitude direction. With reference to FIG. 14, reference numeral 33 denotes an optical recording medium on which digital data, which are mark-width-modulated so as to make the track recording density constant, are recorded; reference numeral 34 denotes a reproduction means for reproducing the digital data recorded on the optical recording medium 33 to output an optical disc reproduction signal; reference numeral 2 denotes a waveform equalization means for emphasizing a high frequency component of the optical disc reproduction signal; reference numeral 3 denotes an analog-to-digital (A/D) converter for sampling the optical disc reproduction signal in which the high frequency component is emphasized, to convert the signal into a multi-bit sampling signal; reference numeral 35 denotes an offset correction means for correcting an offset component in the amplitude direction, which is included in the sampling signal; reference numeral 36 denotes a transversal filter for multi-valuing the sampling signal outputted from the offset correction means 35, by partial response equalization; reference numeral 37 denotes a tap weight coefficient setting means for supplying weight coefficients to taps constituting the transversal filter 36; reference numeral 38 denotes a Viterbi decoder for demodulating the output signal from the transversal filter 36 into binarized digital data; reference numeral 39 denotes a zero cross length detector for detecting a zero cross position where the output signal from the offset correction means 35 crosses the zero level, and counting the number of samples between two adjacent zero cross positions; reference numeral 40 denotes a frequency error detector for determining the amount of frequency error for generating a reproduction clock synchronized with the sampling signal, on the basis of the output from the zero cross length detector 39; reference numeral 41 denotes a phase comparator for detecting the amount of phase error between the clock component of the sampling signal and the reproduction clock, on the basis of the phase of the output signal from the offset correction means 35; reference numeral 42 denotes a frequency control loop filter for performing frequency control up to a region where the reproduction clock can be synchronized with the sampling clock, by using the amount of frequency error; reference numeral 43 denotes a phase control loop filter for performing phase control so that the reproduction clock is synchronized with the sampling signal, by using the amount of phase error; reference numerals 44a and 44b denote digital-to-analog (D/A) converters for converting the signals outputted from the phase control loop filter 43 and the frequency control loop filter 42 into analog signals, respectively; and reference numeral 45 denotes a voltage controlled oscillator (VCO) for generating a reproduction clock on the basis of the analog signals outputted from the D/A converters 44a and 44b. 
Next, a description will be given of the operation of the conventional digital data reproduction apparatus constructed as described above, with reference to FIGS. 14 and 15(a)–15(d). FIGS. 15(a)–15(d) are diagrams illustrating recorded data (15(a)) and waveforms of output signals from the respective output stages (15(b)–15(d)) of the conventional digital data reproduction apparatus.
Conventionally, digital data as shown in FIG. 15(a) are recorded on the optical recording medium 33 so that the track recording density is kept constant. It is assumed that the recorded digital data are data in which the number of continuous 0 s or 1 s is restricted within a range from three to fourteen, like in the 8–16 modulation method. Since, in the optical disc reproduction signal obtained by reproducing the digital data with the reproduction means 34, interference occurs according to an increase in the recording density of the digital data along the track direction, a higher frequency component has more attenuation of amplitude, as shown in FIG. 15(a). So, the optical disc reproduction signal outputted from the reproduction means 34 is amplified by a preamplifier (not shown) and, thereafter, corrected by the waveform equalization means 2 so as to emphasize the higher frequency component. The optical disc reproduction signal in which the higher frequency component is emphasized is shown in FIG. 15(b). Next, the A/D converter 3 for converting an analog signal into a digital signal converts the optical disc reproduction signal shown in FIG. 15(b) into a multi-bit sampling signal. When the phase of the reproduction clock and the phase of the clock component of the sampling signal are synchronized with each other, sampling data (sampling signal) as shown in FIG. 15(c) are obtained. The sampling data shown in FIG. 15(c) are particularly suited to the PRML signal processing method.
The PRML signal processing method will be described as follows. In a reproduction system where the amplitude of a high frequency component is degraded and the signal-noise ratio is increased as the recording density is increased in the track recording direction, a partial response method for realizing a reproduction system that needs no high frequency component by intentionally adding a waveform interference is combined with a maximum likelihood decoding method for estimating a sequence of the maximum likelihood by probability calculation considering the waveform interference, thereby to improve the quality of reproduced data.
Next, the digital signal sampled by the A/D converter 3 is inputted to the offset correction means 35 to correct an offset component in the amplitude direction which is included in the sampling signal. Then, the offset-corrected sampling signal is subjected to partial response equalization by the transversal filter 36. As shown in FIG. 15(d), the partial-response-equalized signal is multi-valued. Further, the weight coefficients of the taps constituting the transversal filter 36 are determined by the tap weight coefficient setting means 37, using the LMS (Least Mean Square) algorithm which minimizes a root-mean-square value of an equalization error. The output signal from the transversal filter 36 is binarized and then demodulated to digital data, by the Viterbi decoder 38 that is a kind of a maximum likelihood decoder.
The reproduction clock to be used by the A/D converter 3 for sampling is controlled as follows.
The zero cross length detector 39 detects zero cross points at which the output signal from the offset correction means 35 crosses the zero level, and counts the number of samples between two adjacent zero cross points. The frequency error detector 40 detects a sync pattern length and a sync pattern detection cycle in a predetermined period of time by using the output from the zero cross length detector 39, and determines the amount of frequency error for performing frequency control of the reproduction clock. Then, the frequency control loop filter 42 performs frequency control up to a region where the reproduction clock can be synchronized with the clock component of the sampling signal, by using the amount of frequency error outputted from the frequency error detector 40, and the D/A converter 44b converts the output signal from the loop filter 42 into an analog signal.
On the other hand, the phase comparator 41 detects phase information of the sampling signal by using the output signal from the offset correction means 35, and determines the amount of phase difference for performing phase sync control between the reproduction clock and the sampling signal. Then, the phase control loop filter 43 performs phase control so that the reproduction clock is synchronized with the clock component of the sampling signal, by using the amount of phase difference outputted from the phase comparator 41, and the D/A converter 44a converts the output signal from the loop filter 43 into an analog signal.
Thereafter, the VCO 45 generates a reproduction clock synchronized with the sampling signal, on the basis of the output signal from the D/A converter 44b, which has been frequency-controlled so that the reproduction clock can be synchronized with the clock component of the sampling signal and then converted into an analog signal, and the output signal from the D/A converter 44a, which has been phase-controlled so that the reproduction clock is synchronized with the sampling signal and then converted into an analog signal.
Through the above-mentioned series of operations, the phase of the reproduction clock can be synchronized with the phase of the clock component of the digital data recorded on the optical disc 33. Hereinafter, the frequency of this clock component is referred to as a channel bit frequency. Further, since the PRML signal processing method is applicable, the digital data recorded on the optical disc 33 can be reproduced with high stability and high accuracy.
In the conventional digital data reproduction apparatus constructed as described above, the optical disc reproduction signal outputted from the optical recording medium 33 is sampled by the A/D converter 3 using the clock synchronized with the clock component of the optical disc reproduction signal, and then the sampling signal is subjected to the PRML signal processing to demodulate the digital data. Further, the PLL (Phase Locked Loop) circuit, the FIR (Finite Impulse Response) filter, and the Viterbi decoder, which are the components of the digital data reproduction apparatus, are operated with the channel bit frequency.
However, when data demodulation employing the PRML signal processing is carried out by using the reproduction clock synchronized with the clock component of the digital data recorded on the optical recording medium 33, since the frequency of the reproduction clock is increased during high-speed reproduction, power consumption of the digital circuit is undesirably increased depending on the frequency.
In order to prevent the undesired increase in power consumption during high-speed reproduction, data demodulation using a reproduction clock that is synchronized with half of the channel bit frequency is carried out. In the case where the frequency of the reproduction clock is half the channel bit frequency, loss of data occurs in the time direction when the optical disc reproduction signal is sampled by the A/D converter 3. That is, in the conventional method where only the sampling signal obtained by sampling with the reproduction clock is subjected to phase sync control and offset correction in the amplitude direction and then data demodulation is performed using the signal, the amount of data in the time direction is degraded due to that the frequency of the reproduction clock used for sampling is halved. Since this degradation causes degradation in performance during phase sync control or offset correction, sufficient reproduction performance cannot be maintained. Consequently, it is impossible for the conventional digital data reproduction apparatus to achieve both of a reduction in power consumption and an increase in reproduction performance, by only halving the frequency of the reproduction clock to be used for sampling.